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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit
sequentially prefetches instructions from memory. As long as the prefetch queue is partially full,
the Execution Unit fetches instructions.
2.1.3
General Registers
The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The
general registers are subdivided into two sets of four registers. These sets are the data registers
(also called the H & L group for high and low) and the pointer and index registers (also called the
P & I group).
Data
Group
Pointer
and
Index
Group
2-4
H
15
8 7
AX
AH
BX
BH
CX
CH
DX
DH
SP
BP
SI
DI
Figure 2-3. General Registers
L
0
Accumulator
AL
Base
BL
Count
CL
Data
DL
Stack Pointer
Base Pointer
Source Index
Destination Index
A1033-0A
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