Intel 80C186EA User Manual page 407

INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-5. Abbreviations for Mnemonic Encoding Matrix
Abbr Definition
b byte operation
d direct
f from CPU register
i immediate
Byte 2
mod 000 r/m
mod 001 r/m
mod 010 r/m
mod 011 r/m
mod 100 r/m
mod 101 r/m
mod 110 r/m
mod 111 r/m
mod and r/m determine the Effective Address (EA) calculation. See Table D-1 for definitions.
D-22
Abbr Definition
ia immediate to accumulator
id indirect
is immediate byte, sign extended
l long (intersegment)
Immed Shift
ADD
OR ROR
ADC
SBB
AND SHL/SAL
SUB
XOR
CMP
Abbr Definition
m memory
r/m EA is second byte
si short intrasegment
sr segment register
Grp1
ROL TEST
—
RCL NOT
RCR NEG
MUL
SHR IMUL
— DIV
SAR IDIV
Abbr Definition
t to CPU register
v variable
w word operation
z zero
Grp2
INC
DEC
CALL id
CALL l, id
JMP id
JMP i, id
PUSH
—