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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
General
Registers
AH
BH
CH
DH
Temporary
Registers
ALU
Flags
Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU
2.1.1
Execution Unit
The Execution Unit executes all instructions, provides data and addresses to the Bus Interface
Unit and manipulates the general registers and the Processor Status Word. The 16-bit ALU within
the Execution Unit maintains the CPU status and control flags and manipulates the general reg-
isters and instruction operands. All registers and data paths in the Execution Unit are 16 bits wide
for fast internal transfers.
2-2
AL
BL
CL
DL
SP
BP
SI
DI
ALU Data Bus
(16 Bits)
EU
Control
System
Execution Unit
(EU)
Address Bus (20 Bits)
Σ
Data
(16 Bits)
CS
DS
SS
ES
IP
Internal
Communications
Registers
Bus
Control
Logic
Instruction Queue
1 2 3 4 5 6
Q Bus
(8 Bits)
Bus Interface Unit
(BIU)
Bus
External
Bus
A1012-0A
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