Table of Contents
Advertisement
BUS INTERFACE UNIT
CLKOUT
HOLD
HLDA
AD15:0
DEN
RD, WR, BHE,
DT / R, S2:0,
A19:16
3.8
BUS CYCLE PRIORITIES
The BIU arbitrates requests for bus cycles from the Execution Unit, the integrated peripherals
(e.g., Interrupt Control Unit) and external bus masters (i.e., bus hold requests). The list below
summarizes the priorities for all bus cycle requests (from highest to lowest).
1.
Instruction execution read/write following a non-pipelined effective address calculation.
2.
Refresh bus cycles.
3.
Bus hold request.
4.
Single step interrupt vectoring sequence.
5.
Non-Maskable interrupt vectoring sequence.
3-46
1
2
NOTES:
1.
T
: HOLD recognition setup to clock low
CLIS
2.
: HOLD internally synchronized
3.
T
: Clock low to HLDA low
CLOV
4.
T
: Clock high to signal active (high or low)
CHOV
5.
T
: Clock low to signal active (high or low)
CLOV
Figure 3-38. Exiting HOLD
4
3
5
A1099-0A
Advertisement
Table of Contents
