Table of Contents
Advertisement
BUS INTERFACE UNIT
CLKOUT
ALE
S2:0
AD15:0
RD / WR
CLKOUT
Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T-
states labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pending. Multiple
T3 states occur to generate wait states. The TW symbol represents a wait state.
The operation of a bus cycle can be separated into two phases:
•
Address/Status Phase
•
Data Phase
3-8
T4
T1
Valid Status
Address
Figure 3-6. Typical Bus Cycle
TN
Falling
Edge
Phase 1
(Low Phase)
Figure 3-7. T-State Relation to CLKOUT
T2
T3
Data
Rising
Edge
Phase 2
(High Phase)
T4
A1507-0A
A1111-0A
Advertisement
Table of Contents
