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CLOCK GENERATION AND POWER MANAGEMENT
5.2.2.2
Leaving Powerdown Mode
An NMI or reset returns the processor to Active mode. If the device leaves Powerdown mode by
an NMI, a delay must follow the interrupt request to allow the crystal oscillator to stabilize before
gating it to the internal phase clocks.An external timing pin sets this delay as described below.
Leaving Powerdown by an NMI does not clear the PWRDN bit in the Power Control Register. A
reset also takes the processor out of Powerdown mode. Since the oscillator is off, the user should
follow the oscillator cold start guidelines (see "Reset and Clock Synchronization" on page 5-6).
The Powerdown timer circuit (Figure 5-13) has a PDTMR pin. Connecting this pin to an external
capacitor gives the user control over the gating of the crystal oscillator to the internal clocks. The
strong P-channel device is always on except during exit from Powerdown mode. This pullup
keeps the powerdown capacitor C
the circuit turns on the feedback inverter on the crystal oscillator and oscillation starts.
The Schmitt trigger connected to the PDTMR pin asserts the internal OSC_OK signal when the
voltage at the pin drops below its switching threshold. The OSC_OK signal gates the crystal os-
cillator output to the internal clock circuitry. One CLKOUT cycle runs before the internal clocks
turn back on. It takes two additional CLKOUT cycles for an NMI request to reach the CPU and
another six clocks for the vector to be fetched.
PDTMR Pin
C PD
5-18
charged up to V
PD
Strong P-Channel
Pullup
Weak N-Channel
Pulldown
Figure 5-13. Powerdown Timer Circuit
. C
discharges slowly. At the same time,
CC
PD
0, Except when leaving
Powerdown
Exit Powerdown
OSC_OK
A1122-0A
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