Refresh Operation And Bus Hold - Intel 80C186EA User Manual

REFRESH CONTROL UNIT
_exercise_ram:
_config_rcu
lib_80186
Example 7-1. Initializing the Refresh Control Unit (Continued)
7.8

REFRESH OPERATION AND BUS HOLD

When another bus master controls the bus, the processor keeps HLDA active as long as the
HOLD input remains active. If the Refresh Control Unit generates a refresh request during bus
hold, the processor drives the HLDA signal inactive, indicating to the current bus master that it
wishes to regain bus control (see Figure 7-9). The BIU begins a refresh bus cycle only after the
alternate master removes HOLD. The user must design the system so that the processor can re-
gain bus control. If the alternate master asserts HOLD after the processor starts the refresh cycle,
the CPU will relinquish control by asserting HLDA when the refresh cycle is complete.
7-12
mov dx, RFBASE
mov ax, _dram_addr
out dx, al
mov dx, RFTIME
mov ax, _clock_time
out dx, al
mov dx, RFCON
mov ax, Enable
out dx, al
mov cx, 8
xor di, di
mov word ptr [di], 0
loop _exercise_ram
pop di
pop dx
pop cx
pop ax
pop bp
ret
endp
ends
end
;set upper 7 address bits
;set clock pre_scaler
;Enable RCU
;8 dummy cycles are
;required by DRAMs
;before actual use
;restore saved registers
;restore caller's bp