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Register Name:
Register Mnemonic:
Register Function:
15
U
U
U
U
1
1
1
1
9
8
7
6
Bit
Bit Name
Mnemonic
U19:13
Start
Address
R2
Bus Ready
Disable
R1:0
Wait State
Value
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. A starting address
other than an integer multiple of the block size defined in the MPCS register
causes unreliable chip-select operation. (See Table 6-5 on page 6-14 for details.)
Reading this register and the MPCS register (before writing them) enables the
MCS chip-selects; however, none of the programmable fields will be properly ini-
tialized.
MCS Control Register
MMCS
Controls the operation of the MCS chip-selects.
U
U
U
1
1
1
5
4
3
Reset
State
XXH
Defines the starting address for the block of
MCS chip-selects. During memory bus cycles,
U19:13 are compared with the A19:13 address
bits. An equal to or greater than result enables
the MCS chip-select. The starting address must
be an integer multiple of the block size defined
in the MPCS register. See Table 6-5 on page
6-14 for additional information.
X
When R2 is clear, bus ready must be active to
complete a bus cycle. When R2 is set, R1:0
control the number of bus wait states and bus
ready is ignored.
3H
R1:0 define the minimum number of wait states
inserted into the bus cycle.
Figure 6-7. MMCS Register Definition
CHIP-SELECT UNIT
0
R
R
R
2
1
0
A1143-0B
Function
6-9
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