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INTERRUPT CONTROL UNIT
8.3.2.2
Interrupts That Share a Single Source
Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit. (For
example, the three timers share a single input.) Although these interrupts share an input, each has
its own interrupt vector. (For example, when a Timer 0 interrupt occurs, the Timer 0 interrupt
handler is executed.) This section uses the three timers as an example to describe how these in-
terrupts are prioritized and serviced.
The Interrupt Status register acts as a second-level request register to process the timer interrupts.
It contains a bit for each timer interrupt. When a timer interrupt occurs, both the individual Inter-
rupt Status register bit and the shared Interrupt Request register bit are set. From this point, the
interrupt is processed like any other interrupt source.
When the shared interrupt is acknowledged, the timer interrupt with the highest priority (see Ta-
ble 8-1 on page 8-3) at that time is serviced first and that timer's Interrupt Status bit is cleared.
If no other timer Interrupt Status bits are set, the shared Interrupt Request bit is also cleared. If
other timer interrupts are pending, the Interrupt Request bit remains set.
When the timer interrupt is acknowledged, the shared In-Service bit is set. No other timer inter-
rupts can occur when the In-Service bit is set. If a second timer interrupt occurs while another
timer interrupt is being serviced, the second interrupt remains pending until the interrupt handler
for the first interrupt finishes and clears the In-Service bit. (This is true even if the second interrupt
has a higher priority than the first.)
8.3.3
Cascading with External 8259As
For applications that require more external interrupt pins than the number provided on the Inter-
rupt Control Unit, external 8259A modules can be used to increase the number of external inter-
rupt pins. The cascade mode of the Interrupt Control Unit supports the external 8259As. The
INT2/INTA0 and INT3/INTA1 pins can serve either of two functions. Outside cascade mode,
they serve as external interrupt inputs. In cascade mode, they serve as interrupt acknowledge out-
puts. INTA0 is the acknowledge for INT0, and INTA1 is the acknowledge for INT1. (See Figure
8-2.)
The INT2/INTA0 and INT3/INTA1 pins are inputs after reset until the pins are configured as out-
puts. The pullup resistors ensure that the INTA pins never float (which would cause a spurious
interrupt acknowledge to the 8259A). The value of the resistors must be high enough to prevent
excessive loading on the pins.
8-7
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