Intel 80C186EA User Manual page 78

Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = 1
NMI Divide
Push PSW, CS, IP
Fetch Divide Error Vector
Push PSW, CS, IP
Fetch NMI Vector
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = ???
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X
Push PSW, CS, IP
Fetch Single Step Vector
Execute Single Step Service Routine
Figure 2-30. Simultaneous NMI, Single Step and Maskable Interrupt
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Timer Interrupt
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Push PSW, CS, IP
Fetch Single Step Vector
Execute Single Step
Service Routine
IRET
IRET
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X
A1034-0A
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