Table of Contents
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INDEX
P
Packed BCD, defined, 2-37
Packed decimal, defined, 11-7
Parity Flag (PF), 2-7, 2-9
PCB Relocation Register, 4-1, 4-3, 4-6
and math coprocessing, 11-2
PDTMR pin, 5-18
Peripheral Control Block (PCB), 4-1
accessing, 4-4
and DMA Unit, 10-3
and F-Bus operation, 4-5
base address, 4-6–4-7
bus cycles, 4-4
READY signals, 4-4
reserved locations, 4-6
wait states, 4-4
Peripheral control registers, 4-1, 4-6
Pointer, defined, 2-37
Poll register, 8-9, 8-19, 8-20
Poll Status register, 8-9, 8-19, 8-20, 8-21
Polling, 8-1, 8-9
POPA instruction, A-1
Power consumption‚ reducing, 3-28, 5-23
Power Control Register, 5-12
Power management, 5-10–5-23
Power management modes
and HALT bus cycles, 3-28, 3-31
compared, 5-23
Powerdown mode, 5-16–5-19, 7-2
and bus cycles, 5-16
control register, 5-12
entering, 5-17
exiting, 5-18–5-19
exiting HALT bus cycle, 3-34
initialization code, 5-15–5-18
Power-Save mode, 5-19–5-22, 7-2
and DRAM refresh rate, 5-21
and refresh interval, 7-7
control register, 5-20
entering, 5-19
exiting, 5-21
initialization code, 5-21–5-22
Power-Save Register, 5-20
Priority Mask register, 8-17, 8-18, 8-28
Processor control instructions, 2-27
Processor Status Word (PSW), 2-1, 2-7, 2-41
bits defined, 2-7, 2-9
Index-6
flag storage formats, 2-19
reset status, 2-7
Program transfer instructions, 2-23–2-24
conditional transfers, 2-24, 2-26
interrupts, 2-26
iteration control, 2-25
unconditional transfers, 2-24
PUSH instruction, A-8
PUSHA instruction, A-1
Q
Queue status signals, 3-40
R
RCL instruction, A-10
RCR instruction, A-10
Read bus cycles‚ See Bus cycles
READY
and chip-selects, 6-15
and normally not-ready signal, 3-17–3-18
and normally ready signal, 3-16–3-17
and PCB accesses, 4-4
and wait states, 3-13–3-18
implementation approaches, 3-13
timing concerns, 3-17
Real, defined, 11-7
Real-time clock, code example, 9-17–9-20
Refresh address, 7-4
Refresh Base Address Register (RFBASE), 7-8
Refresh bus cycle‚ See Bus cycles
Refresh Clock Interval Register (RFTIME), 7-7,
7-8
Refresh Control Register (RFCON), 7-9, 7-10
Refresh Control Unit (RCU), 7-1–7-13
and bus hold protocol, 7-12–7-13
and Powerdown mode, 7-2
and Power-Save mode, 5-19, 7-2, 7-7
block diagram, 7-1
bus latency, 7-7
calculating refresh interval, 7-7
control registers, 7-7–7-10
initialization code, 7-10
operation, 7-2
overview, 7-2–7-4
programming, 7-7–7-11
relationship to BIU, 7-1
Register operands, 2-27
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