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Many input signals to an embedded processor are asynchronous. Asynchronous signals do not re-
quire a specified setup or hold time to ensure the device does not incur a failure. However, asyn-
chronous setup and hold times are specified in the data sheet to ensure recognition. Associated
with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchro-
nous signal and synchronizes it to the internal operating clock. The output of the synchronizing
circuit is then safely routed to the logic units.
Asynchronous
Input
NOTES:
1. First latch sample clock, can be phase 1 or phase 2 depending on pin function.
2. Second latch sample clock, opposite phase of first latch sample clock
(e.g., if first latch is sampled with phase 1, the second latch is sampled with phase 2).
B.1
WHY SYNCHRONIZERS ARE REQUIRED
Every data latch requires a specific setup and hold time to operate properly. The duration of the
setup and hold time defines a window during which the device attempts to latch the data. If the
input makes a transition within this window, the output may not attain a stable state. The data
sheet specifies a setup and hold window larger than is actually required. However, variations in
device operation (e.g., temperature, voltage) require that a larger window be specified to cover
all conditions.
Should the input to the data latch make a transition during the sample and hold window, the out-
put of the latch eventually attains a stable state. This stable state must be attained before the sec-
ond stage of synchronization requires a valid input. To synchronize an asynchronous signal, the
circuit in Figure B-1 samples the input into the first latch, allows the output to stabilize, then sam-
ples the stabilized value into a second latch. With the asynchronous signal resolved in this way,
the input signal cannot cause an internal device failure.
INPUT SYNCHRONIZATION
D
Q
First
Latch
1
Figure B-1. Input Synchronization Circuit
APPENDIX B
D
Q
Second
Latch
2
Synchronized
Output
A1007-0A
B-1
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