Intel 80C186EA User Manual page 69

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Memory
Table
Address
Entry
3FE CS
3FC IP
82
CS
80
IP
7E
CS
7C
IP
52 CS
50 IP
4E CS
4C IP
4A CS
48 IP
46 CS
44 IP
42 CS
40 IP
3E CS
3C IP
3A CS
38 IP
36 CS
34 IP
32 CS
30 IP
2 Bytes
When an interrupt is acknowledged, a common event sequence (Figure 2-26) allows the proces-
sor to execute the interrupt service routine.
1. The processor saves a partial machine status by pushing the Processor Status Word onto
the stack.
2-40
Vector Memory
Definition Address
2E
Type 255
2C
User
2A
Available
28
26
Type 32
24
22
Type 31
20
1E
Reserved
1C
1A
Type 20
18
16
Type 19 - Timer 2
14
12
Type 18 - Timer 1
10
0E
Type 17 - Reserved
0C
0A
Type 16 - Numerics
08
06
Type 15 - INT3
04
02
Type 14 - INT2
00
Type 13 - INT1
Type 12 - INT0
CS = Code Segment Value
IP = Instruction Pointer Value
Figure 2-25. Interrupt Vector Table
Table Vector
Entry Definition
CS
Type 11 - DMA1
IP
CS
Type 10 - DMA0
IP
CS
Type 9 - Reserved
IP
CS
Type 8 - Timer 0
IP
CS
Type 7 - ESC Opcode
IP
CS
Type 6 - Unused
IP
Opcode
CS
Type 5 - Array
IP
Bounds
CS
Type 4 - Overflow
IP
CS
Type 3 - Breakpoint
IP
CS
Type 2 - NMI
IP
CS
Type 1 - Single-Step
IP
CS
Type 0 - Divide Error
IP
2 Bytes
A1009-02