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CLOCK GENERATION AND POWER MANAGEMENT
Register Name:
Register Mnemonic:
Register Function:
15
P
S
E
N
Bit
Mnemonic
PSEN
Power Save
Enable
F1:0
Clock
Division
Factor
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
5-20
Power Save Register
PWRSAV
Enables and sets clock division factor.
Reset
Bit Name
State
0H
0H
Figure 5-14. Power-Save Register
Function
Setting this bit enables Power Save mode and
divides the internal operating clock by the value
defined by F1:0. Clearing this bit disables
Power-Save mode and forces the CPU to
operate at full speed. PSEN is automatically
cleared whenever an interrupt occurs.
These bits control the clock division factor used
when Power Save mode is enabled. The
allowable values are listed below:
F1 F0 Divisor
0 0 By 1 (undivided)
0 1 By 4
1 0 By 8
1 1 By 16
0
F
F
1
0
A1130-0A
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