Dma Latency - Intel 80C186EA User Manual

10.3.2 DMA Latency

DMA Latency is the delay between a DMA request being asserted and the DMA cycle being run.
The DMA latency for a channel is controlled by many factors:
•
Bus HOLD — Bus HOLD takes precedence over internal DMA requests. Using bus HOLD
will degrade DMA latency.
•
LOCKed Instructions — Long LOCKed instructions (e.g., LOCK REP MOVS) will
monopolize the bus, preventing access by the DMA Unit.
•
Inter-channel Priority Scheme — Setting a channel at low priority will affect its latency.
The minimum latency in all cases is four CLKOUT cycles. This is the amount of time it takes to
synchronize and prioritize a request.
10.3.3 DMA Transfer Rates
The maximum DMA transfer rate is a function of processor operating frequency and synchroni-
zation mode. For unsynchronized and source-synchronized transfers, the 80C186 Modular Core
can transfer two bytes every eight CLKOUT cycles. For destination-synchronized transfers, the
addition of two idle T-states reduces the bandwidth by two clocks per word.
Maximum DMA transfer rates (in Mbytes per second) for the 80C186 Modular Core are calcu-
lated by the following equations, where F
For unsynchronized and source-synchronized transfers:
×
0.25 F
CPU
For destination-synchronized transfers:
×
0.20 F
CPU
Because of its 8-bit data bus, the 80C188 Modular Core can transfer only one byte per DMA cy-
cle. Therefore, the maximum transfer rates for the 80C188 Modular Core are half those calculated
by the equations for the 80C186 Modular Core.
DIRECT MEMORY ACCESS UNIT
is the CPU operating frequency (in megahertz).
CPU
10-21