Implementing A Power Management Scheme - Intel 80C186EA User Manual

5.2.4

Implementing a Power Management Scheme

Table 5-2 summarizes the power management options available to the user. With three ways
available to reduce power consumption, here are some guidelines:
•
Powerdown mode reduces power consumption by several orders of magnitude. If the
application goes into and out of Powerdown frequently, the power reduction can probably
offset the relatively long intervals spent leaving Powerdown mode.
•
If background CPU tasks are usually necessary and the overhead of reprogramming
peripherals is not severe, Power-Save mode can "tune" the clock rate to the best value.
Remember that current varies linearly with respect to frequency.
•
Idle mode fits DMA-intensive and interrupt-intensive (as opposed to CPU-intensive) appli-
cations perfectly.
The processor can operate in Power-Save mode and Idle mode concurrently. With Idle mode
alone, rated power consumption typically drops a third or more. Power-Save mode multiplies that
reduction further according to the selected clock divisor.
Overall power consumption has two parts: switching power dissipated by driving loads such as
the address/data bus, and device power dissipated internally by the microprocessor whether or not
it is connected to external devices. A power management scheme should consider loading as well
as the raw specifications in the processor's data sheet.
Table 5-2. Summary of Power Management Modes
Relative
Mode
Power
Active Full
Idle Low
Power-Save Adjustable
Powerdown Lowest
If an NMI or external maskable interrupt service routine is used to enter a
power management mode, the interrupt request signal should be deasserted
before entering the power management mode.
CLOCK GENERATION AND POWER MANAGEMENT
Typical
Power
250 mW at 16 MHz
175 mW at 16 MHz
125 mW at 16/2 MHz Moderate to High
250 µW Low to Moderate
NOTE
User
Overhead Advantage
— Full-speed operation
Low Peripherals are unaffected
Code execution continues
Long battery life
Chief
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