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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Bit Name
Mnemonic
OF
Overflow Flag
DF
Direction Flag
Interrupt
IF
Enable Flag
TF
Trap Flag
SF
Sign Flag
ZF
Zero Flag
AF
Auxiliary Flag
PF
Parity Flag
CF
Carry Flag
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Processor Status Word
PSW (FLAGS)
Posts CPU status information.
O
D
I
T
S
F
F
F
F
F
Reset
State
0
If OF is set, an arithmetic overflow has occurred.
If DF is set, string instructions are processed high
0
address to low address. If DF is clear, strings are
processed low address to high address.
If IF is set, the CPU recognizes maskable interrupt
0
requests. If IF is clear, maskable interrupts are
ignored.
0
If TF is set, the processor enters single-step mode.
If SF is set, the high-order bit of the result of an
0
operation is 1, indicating it is negative.
0
If ZF is set, the result of an operation is zero.
If AF is set, there has been a carry from the low
nibble to the high or a borrow from the high nibble
0
to the low nibble of an 8-bit quantity. Used in BCD
operations.
If PF is set, the result of an operation has even
0
parity.
If CF is set, there has been a carry out of, or a
0
borrow into, the high-order bit of the result of an
instruction.
Figure 2-5. Processor Status Word
Z
A
P
F
F
F
Function
0
C
F
A1035-0A
2-9
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