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Register Name:
Register Mnemonic:
Register Function:
15
M
M
M
6
5
4
Bit
Bit Name
Mnemonic
M6:0
Block Size
EX
Pin Selector
MS
Bus Cycle
Selector
R2
Bus Ready
Disable for
PCS6:4
R1:0
Wait State
Value for
PCS6:4
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. A starting address
other than an integer multiple of the block size defined in this register causes
unreliable chip-select operation. Reading this register and the MMCS or PACS
register (before writing them) enables the associated chip-selects; however, none
of the programmable fields will be properly initialized.
MCS and PCS Alternate Control Register
MPCS
Controls operation of the MCS and PCS chip-
selects.
M
M
M
M
E
3
2
1
0
X
Reset
State
XXH
Defines the block size for the MCS chip-selects.
Table 6-5 on page 6-14 lists allowable values.
XH
Setting EX configures PCS6:5 as chip-selects.
Clearing EX configures the pins as latched
address bits A2:A1.
XH
Clearing MS activates PCS6:0 for I/O bus
cycles. Setting MS activates PCS6:0 for
memory bus cycles.
X
Applies only to PCS6:4. When R2 is clear, bus
ready must be active to complete a bus cycle.
When R2 is set, R1:0 control the number of bus
wait states and bus ready is ignored.
3H
Apply only to PCS6:4. R1:0 define the minimum
number of wait states inserted into the bus
cycle.
Figure 6-9. MPCS Register Definition
CHIP-SELECT UNIT
M
R
S
2
Function
0
R
R
1
0
A1144-0A
6-11
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