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CLOCK GENERATION AND POWER MANAGEMENT
Reset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RES-
IN input during power supply and oscillator startup. The processor's pins assume their reset pin
states a maximum of 28 CLKIN periods after CLKIN and V
stabilize. Assert RESIN 4 addi-
CC
tional CLKIN periods after the device pins assume their reset states.
Applying RESIN when the device is running constitutes a warm reset (see Figure 5-7). In this
case, assert RESIN for at least 4 CLKOUT periods. The device pins will assume their reset states
on the second falling edge of CLKIN following the assertion of RESIN.
V
cc
-t
RC
100k typical
V
= V
1 - e
c(t)
RESET IN
RESIN
1µF typical
A1128-0A
Figure 5-5. Simple RC Circuit for Powerup Reset
The processor exits reset identically in both cases. The falling RESIN edge generates an internal
RESYNC pulse (see Figure 5-8), resynchronizing the divide-by-two internal phase clock. The
clock generator samples RESIN on the falling CLKIN edge. If RESIN is sampled high while
CLKOUT is high, the processor forces CLKOUT low for the next two CLKIN cycles. The clock
essentially "skips a beat" to synchronize the internal phases. If RESIN is sampled high while
CLKOUT is low, CLKOUT is already in phase.
5-7
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