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Register Name:
Register Mnemonic:
Register Function:
15
U
U
1
1
7
6
Bit
Bit Name
Mnemonic
U17:10
Start
Address
R2
Bus Ready
Disable
R1:0
Wait State
Value
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. Programming
U17:10 with values other than those shown in Table 6-2 on page 6-12 results in
unreliable chip-select operation. Reading this register (before writing it) enables
the chip-select; however, none of the programmable fields will be properly initial-
ized.
UCS Control Register
UMCS
Controls the operation of the UCS chip-select.
U
U
U
U
U
1
1
1
1
1
5
4
3
2
1
Reset
State
0FFH
Defines the starting address for the chip-select.
During memory bus cycles, U17:10 are
compared with the A17:10 address bits. An
equal to or greater than result enables the UCS
chip-select if A19:18 are both one. Table 6-2 on
page 6-12 lists the only valid programming
combinations.
0H
When R2 is clear, bus ready must be active to
complete a bus cycle. When R2 is set, R1:0
control the number of bus wait states and bus
ready is ignored.
3H
R1:0 define the minimum number of wait states
inserted into the bus cycle.
Figure 6-5. UMCS Register Definition
CHIP-SELECT UNIT
U
R
1
2
0
Function
0
R
R
1
0
A1141-0A
6-7
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