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The 80C186 Modular Core has a single maskable interrupt input. (See "Interrupts and Exception
Handling" on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities be-
yond a single input. To fulfill this function, the Interrupt Control Unit operates in either of two
modes: Master or Slave.
In Master mode, the ICU controls the maskable interrupt input to the CPU. Interrupts can origi-
nate from the on-chip peripherals and from four external interrupt pins. The ICU synchronizes
and prioritizes all interrupt sources and presents the correct interrupt type vector to the CPU. (See
Figure 8-1.) Most systems use master mode.
In Slave mode, an external 8259A module controls the maskable interrupt input to the CPU and
acts as the master interrupt controller. The ICU processes only those interrupts from the on-chip
peripherals and acts as an interrupt input to the 8259A. (See Figure 8-15 on page 8-24.) This mode
can be useful in larger system designs.
The Interrupt Control Unit has the following features:
•
Programmable priority of each interrupt source
•
Individual masking of each interrupt source
•
Nesting of interrupt sources
•
Support for polled operation
•
Support for cascading external 8259A modules to expand external interrupt sources
8.1
FUNCTIONAL OVERVIEW
All microcomputer systems must communicate in some way with the external world. A typical
system might have a keyboard, a disk drive and a communications port, all requiring CPU atten-
tion at different times. There are two distinct ways to process peripheral I/O requests: polling and
interrupts.
Polling requires that the CPU check each peripheral device in the system periodically to see
whether it requires servicing. It would not be unusual to poll a low-speed peripheral (a serial port,
for instance) thousands of times before it required servicing. In most cases, the use of polling has
a detrimental effect on system throughput. Any time used to check the peripherals is time spent
away from the main processing tasks.
INTERRUPT CONTROL UNIT
CHAPTER 8
8-1
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