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INTERRUPT CONTROL UNIT
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
VT2:0
Interrupt
Type
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-18. End-of-Interrupt Register in Slave Mode
8.5.1.3
Other Registers
The Priority Mask register is identical in Slave mode and Master mode. The Interrupt Request,
Interrupt Mask, and In-Service registers retain the same function, but individual bits differ to ac-
commodate the addition of the individual timer interrupts and the deletion of the external inter-
rupts. Figure 8-19 shows the bit positions for Slave mode.
15
Figure 8-19. Request, Mask, and In-Service Registers
8-28
End-of-Interrupt Register (in Slave Mode)
EOI
Used to issue the EOI command
Reset
Bit Name
State
0
Function
Write the three LSBs of the interrupt type (see
Table 8-5) to these bits to issue an EOI
command in slave mode.
T
T
M
M
R
R
2
1
0
V
V
V
T
T
T
2
1
0
A1197-A0
0
D
D
T
M
M
M
A
A
R
0
1
0
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