Intel Xeon Design Manual page 8

Processor with 512 kb l2 cache and intel e7500 chipset platform
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12.5
Intel® P64H2 Power Requirements .................................................................. 185
12.5.1
12.5.2
12.5.3
12.5.4
13
13.1
Processor Schematic Checklist......................................................................... 187
13.2
MCH Schematic Checklist................................................................................. 193
13.3
13.4
13.5
CK408 Schematic Checklist.............................................................................. 209
14
14.1
Processor Checklist .......................................................................................... 211
14.2
Intel® E7500 MCH Layout Checklist................................................................. 213
14.3
Intel® ICH3-S Layout Checklist......................................................................... 216
15
8
Intel® P64H2 Current Requirements ............................................... 185
Intel® P64H2 Decoupling Requirements ......................................... 185
PCIRST# Implementation................................................................. 186
P64H2 Power Sequencing Requirement.......................................... 186
............................................................................................. 187
®
ICH3-S Schematic Checklist ................................................................... 196
®
82870P2 P64H2 Schematic Checklist..................................................... 204
..................................................................................................... 211
............................................................................................................... 221
Design Guide

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