Intel Xeon Design Manual page 194

Processor with 512 kb l2 cache and intel e7500 chipset platform
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Schematic Checklist
Table 13-2. MCH Schematic Checklist (Sheet 2 of 3)
Checklist Items
Hub Interface A
HI[11:0]
11
HI_STBF
HI_STBS
Hub Interface B, C, D
HI[18:0]
HI[21:20]
PSTRBF
PSTRBS
PUSTRBF
PUSTRBS
Clocks, Reset, Miscellaneous Signals
HCLKINP
HLCKINN
CLK66
RSTIN#
Miscellaneous Signals
XORMODE#
Reserved
(Ball B30)
Reserved
(Ball D29)
HIRCOMP_A
HIRCOMP_B
HIRCOMP_C
HIRCOMP_D
HXRCOMP
HYRCOMP
194
Recommendations
• Maximum length of 20" (stripline routing).
• Connect to ICH3-S.
11
• Must NOT have pull-up, pull-down, or series
resistors.
• Maximum length of 20" (stripline routing).
• Connect to P64H2.
• Must not have pull-up, pull-down, or series
resistors.
• Route with a 49.9 Ω ± 1% pull-down resistor to
ground.
• Place 43 Ω series resistor close to CK408B.
• Connect to PCIRST# output of the ICH3-S.
• 4.7 k Ω ± 5% pull-up to VCC_3.3.
• 4.7 k Ω ± 5% pull-up to VCC_3.3.
• 1 k Ω ± 5% pull-down to Ground.
• Tie the MCH RCOMP pin to a 24.9 Ω ± 1% pull-
up to VCC_1.2
• (For Trace Impedance = 50 Ω ± 10%).
• Tie the MCH RCOMP pins to a 24.9 Ω ± 1%
pull-up to VCC_1.2
(For trace impedance = 50 Ω ± 10%).
• Tie the P64H2 RCOMP pins to a 61.9 Ω ± 1%
pull-up to VCC_1.8
(For trace impedance = 50 Ω ± 10%).
• Tie each COMP pin to a 25 Ω ± 1% pull-down
resistor to ground.
Comments
• Refer to
Section
7.3.1.
• Refer to
Section
7.3.1.
• Refer to
Section
7.2.1.
• Refer to
Section
7.2.
• Refer to
Section
4.1.1.
• Refer to
Section
4.1.2.
• Required for normal
operation.
• Required for normal
operation.
• Required for normal
operation.
• Used to calibrate the I/O
Buffers.
• Resistive compensation is
used by the ICH3-S and MCH
to adjust the buffer
characteristics to specific
board characteristic.
• Refer to
Section
7.3.3.
• Used to calibrate the I/O
Buffers.
• Resistive compensation is
used by the P64H2 and MCH
to adjust the buffer
characteristics to specific
board characteristics.
• Refer to
Section
7.2.3.
• This signal is used to calibrate
the Host AGTL+ I/O buffer
characteristics to specific
board characteristics.
• Refer to
Section
5.3.5.
Design Guide

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