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8
7
60
CPU0_VID[4:0]
6,60
+VCC_CPU
D
Q54
2
DP_MODE_5V
S
60
1
G
D
+V5_0
3
3
D
G
1
S
C
Q55
2
6311_FB
NOPOP
2K
5%
+V12
CR40
2
3
1
COIL_P12V_CPU
61
BAT54C
B
Q27
C518
0.1UF
1
G
HIP6601
1
8
UGATE
PHASE
2
7
BOOT
PVCC
Q28
6301_PWM2
3
6
61
PWM
VCC
4
5
GND
LGATE
U51
1
G
C459
1UF
A
6301_ISEN2
61
8
7
6
VRD_OFF_N
+V5_0
C513
0.1UF
HIP6311
CPU0_VID4
1
20
VID4
VCC
CPU0_VID3
2
19
VID3
PGOOD
CPU0_VID2
3
18
6301_PWM4
VID2
PWM4
CPU0_VID1
4
17
6301_ISEN4_R
VID1
ISEN4
CPU0_VID0
5
16
6301_ISEN1_R
VID0
ISEN1
R479
6
15
6301_PWM1
6311_COMP
COMP
PWM1
15K
7
14
6301_PWM2
FB
PWM2
R477
120PF
1%
8
13
6301_ISEN2_R
FS_DIS
ISEN2
121K
9
12
6301_ISEN3_R
C455
GND
ISEN3
10
11
6301_PWM3
VSEN
PWM3
U55
C514
+VCC_CPU
0.1UF
NOPOP
R478
0
+VCC_CPU
Q58
2
2
D
D
1
G
S
S
3
3
Q63
6301_PWM3
2
2
61
D
D
1
G
S
S
3
3
Processor Voltage Regulator circuitry
6
5
4
+V3_3
3
BAT54C
10K
C515
ICH3_VRMPWRGD
0.1UF
55
R820
61
6301_ISEN4
61
4.3K
R822
6301_ISEN1
61
61
4.3K
1
R821
UGATE
61
6301_ISEN2
61
2
BOOT
4.3K
6301_PWM1
3
R823
61
PWM
6301_ISEN3
61
4
GND
61
4.3K
U48
6301_ISEN1
61
+V12
CR39
2
3
1
BAT54C
COIL_P12V_CPU
61
Q25
Q59
2
C517
D
D
0.1UF
1
G
1
G
S
S
3
3
HIP6601
1
8
UGATE
PHASE
2
7
BOOT
PVCC
Q26
Q64
2
3
6
PWM
VCC
4
5
D
D
GND
LGATE
U50
1
G
1
G
S
S
3
3
C458
1UF
6301_ISEN3
61
5
4
3
+V12
L17
1
2
1.9UH
+
+V12
CR37
2
1
COIL_P12V_CPU
61
Q22
Q56
2
D
1
G
1
G
S
3
HIP6601
8
PHASE
7
PVCC
Q29
Q61
2
6
VCC
D
5
LGATE
C457
1
G
1
G
1UF
S
3
CR38
2
3
1
BAT54C
+VCC_CPU
C1573
2
C516
1UF
L14
0.1UF
1
2
400NH
HIP6601
1
UGATE
PHASE
2
BOOT
PVCC
6301_PWM4
3
2
61
PWM
VCC
4
4
GND
LGATE
NOPOP
U49
C1511
100PF
NOPOP
6301_ISEN4
61
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
Folsom, California 095630
3
2
1
COIL_P12V_CPU
+
+
+
+
+
+VCC_CPU
2
L13
D
1
2
400NH
S
3
2
4
D
NOPOP
S
C1509
3
100PF
NOPOP
COIL_P12V_CPU
61
+V12
+VCC_CPU
C1572
1UF
Q23
Q57
2
2
D
D
1
G
1
G
S
S
3
3
8
7
Q24
Q62
2
2
6
D
D
5
C456
1
G
1
G
1UF
S
S
3
3
SHEET
LAST REVISED:
61
03/04/02
2
1
61
D
C
B
A
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