Intel Xeon Design Manual page 261

Processor with 512 kb l2 cache and intel e7500 chipset platform
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8
7
D
C
48
+V12
47
48
47
29
P64H2_1_HA_PWRENA
29
B
+VSBY3_3
14
U82
12
11
13
P64H2_1_HA_FAULTA_N
27,39
74LVC08
7
PCI Hot Plug power controller 133Mhz (slot1) and 100Mhz (slot2) for P64H2#1
A
8
7
6
-V12
15
M12VIN_1
13
SLOT_2_M12V_G
M12VG_1
14
M12VO_1
SLOT_2_M12V
28
M12VIN_2
2
SLOT_1_M12V_G
M12VG_2
1
M12VO_2
SLOT_1_M12V
21
12VIN_1
9
SLOT_2_12V_G
12VG_1
8
12VO_1
SLOT_2_12V
22
12VIN_2
6
SLOT_1_12V_G
12VG_2
7
12VO_2
SLOT_1_12V
12
PWRON_1
3
PWRON_2
P64H2_1_HB_PWRENB
U74
+V3_3
14
U72
13
12
SLOT_1_SMBEN_N
42
74LVC14
7
6
5
4
Route as diff pair
SLOT_2_5V
SLOT_2_5V_S
18
5VISEN_1
19
5VS_1
20
SLOT2_3_5V_G
3V5VG_1
HIP1011D
23
SLOT1_3_5V_G
3V5VG_2
24
SLOT_1_5V_S
5VS_2
SLOT_1_5V
25
5VISEN_2
16
3VISEN_1
17
3VS_1
26
3VS_2
27
3VISEN_2
P64H2_1_HB_FAULTB_N
28,37
P64H2_1_HA_FAULTA_N
27,39
5
4
3
2
SLOT_2_5V
48
3
2
1
S
4
G
D
Q40
+V5_0
5
6
7
8
5
6
7
8
Q39
D
G
4
S
3
2
1
R593
SLOT_1_5V
47
0.005
Route as diff pairs
SLOT_2_3V
SLOT_2_3V
42,48
R594
0.005
SLOT_2_3V_S
3
2
1
S
4
G
D
Q37
+V3_3
5
6
7
8
5
6
7
8
Q38
D
G
4
S
3
2
1
R590
SLOT_1_3V_S
SLOT_1_3V
47
0.005
SLOT_1_3V
Route as diff pair
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
Folsom, California 095630
3
2
1
D
C
B
A
SHEET
LAST REVISED:
39
03/04/02
1

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