Intel Xeon Design Manual page 11

9-20 Critical Dimensions for Component Placement.................................................143
9-21 Termination Plane .............................................................................................145
11-1 Spread Spectrum Modulation Profile.................................................................151
11-2 Impact of Spread Spectrum Clocking on Radiated Emissions ..........................151
11-3 Cancellation of H-fields Through Inverse Currents ...........................................152
11-4 Conceptual Processor Ground Frame...............................................................154
11-5 Retention Mechanism Outline and Ground Pad Detail......................................155
11-6 Retention Mechanism Placement and Keep-Out Overview ..............................156
11-7 EMI Ground Size and Location .........................................................................157
11-8 Retention Mechanism Ground Ring ..................................................................158
12-1 Power Delivery Example ...................................................................................160
12-2 Power Distribution Block Diagrams for Two-Way System Motherboard ...........165
12-3 VRM VID Routing ..............................................................................................167
12-4 Simplified VRD Circuit Example ........................................................................167
12-5 Example Load Line Selection Circuit.................................................................168
12-6 VID Routing .......................................................................................................169
12-7 Power-Up and Power-Down Timing ..................................................................170
12-8 Processor Filter Topology .................................................................................171
12-9 Filter Implementation 1: Using Discrete Resistor ..............................................172
12-10 Filter Implementation 2: No Discrete Resistor...................................................172
12-11 Decoupling Example for a Microstrip Baseboard Design ..................................174
12-12 1206 Capacitor Pad and Via Layouts................................................................174
12-13 GTLREF Divider ................................................................................................175
12-14 Suggested GTLREF Generation .......................................................................176
12-15 MCH Decoupling (Backside View) ....................................................................178
12-16 Filter Topology for VCCA_1.2 (DDR Interface) .................................................179
12-17 Filter Topology for VCCAHI_1.2 (HUB Interface)..............................................179
12-18 Filter Topology for VCCAHI_1.2 (System Bus) .................................................180
12-19 Power Sequencing Requirement for MCH ........................................................180
12-20 Sample 2.5 V Output Enable Control Logic.......................................................181
12-21 Example 1.8 V/3.3 V Power Sequencing Circuit ...............................................182
12-22 Example 3.3 V/V5REF Sequencing Circuitry ....................................................183
12-23 3.3V PCI/PCI-X (VCC_3.3) Capacitor Placement .............................................186
Design Guide 11