Table of Contents
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6-16
DDR VREF Voltage Regulator ............................................................................ 80
6-17
DDR VREF Voltage Divider ................................................................................ 80
6-18
DDR VTerm Plane .............................................................................................. 81
6-19
DIMM Decoupling................................................................................................ 82
7-1
Signal Naming Convention on Both Sides of the Hub Interfaces........................ 83
7-2
Hub Interface 2.0 Length matching ..................................................................... 86
7-3
Hub Interface 2.0 Routing Guidelines for Device Down Solutions ...................... 86
7-4
7-5
Hub Interface 2.0 with Locally Generated Voltage Divider Circuit ...................... 88
7-6
Hub Interface 2.0 RCOMP Circuits ..................................................................... 88
7-7
8-Bit Hub Interface 1.5 Routing........................................................................... 89
7-8
Hub Interface 1.5 Locally Generated Reference Divider Circuits........................ 91
7-9
Hub Interface 1.5 RCOMP Circuits ..................................................................... 91
8-1
Typical PCI/PCI-X Routing.................................................................................. 94
8-2
Typical Hot Plug Routing..................................................................................... 95
8-3
Hot Plug Clock Configuration .............................................................................. 96
8-4
No Hot Plug Clock Configuration ........................................................................ 96
8-5
Loop Clock Configuration.................................................................................... 97
8-6
IDSEL Sample Implementation Circuit................................................................ 98
8-7
Manually-Operated Retention Latch Sensor ..................................................... 101
8-8
Attention Button Implementation ....................................................................... 102
8-9
Tri-State Buffer Circuit Example........................................................................ 104
8-10
MUX Circuit Example ........................................................................................ 105
8-11
Single Slot Parallel SMBus Circuit .................................................................... 106
8-12
Reference Schematic for Single-Slot Parallel Mode ......................................... 107
8-13
Dual Slot Parallel SMBus Circuit....................................................................... 110
8-14
Reference Schematic for Dual-Slot Parallel Mode............................................ 111
8-15
Four Slot Stutter Logic Implementation Example.............................................. 113
8-16
Reference Schematic for Serial Mode .............................................................. 114
8-17
M66EN Isolation Switch Solution ...................................................................... 116
8-18
M66EN Diode Solution...................................................................................... 117
9-1
Combination Host-Side/Device-Side IDE Cable Detection ............................... 120
9-2
Connection Requirements for Primary IDE Connector ..................................... 121
9-3
Connection Requirements for Secondary IDE Connector................................. 122
9-4
Example Speaker Circuit................................................................................... 123
9-5
PCI Bus Layout Example .................................................................................. 124
9-6
Suggested USB Downstream Power Connection ............................................. 126
9-7
Intel® ICH3-S SMBus / SMLink Interface ......................................................... 127
9-8
Unified VCC_3.3 Architecture ........................................................................... 128
9-9
RTCX1 and SUSCLK Relationship ................................................................... 128
9-10
RTC External Circuitry ...................................................................................... 129
9-11
RTC Connection When Not Using Internal RTC ............................................... 129
9-12
A Diode Circuit to Connect RTC External Battery ............................................. 131
9-13
RTCRST# External Circuit ................................................................................ 132
9-14
Platform LAN Connect ..................................................................................... 134
9-15
Point-to-Point Interconnect Guideline ............................................................... 135
9-16
LAN_CLK Routing Example.............................................................................. 136
9-17
Routing a 90 Degree Bend................................................................................ 137
9-18
Ground Plane Separation.................................................................................. 139
9-19
10
®
82562ET/EM Termination ....................................................................... 143
Design Guide
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