Intel Xeon Design Manual page 294

Processor with 512 kb l2 cache and intel e7500 chipset platform
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8
7
D
C
B
See Adaptec* AIC-7902 Design-In Handbook for
A
up-to-date information regarding implementation of this subsystem
8
7
6
5
Adaptec* AIC-7902
SCSI_SEEDO
SCSI_SEEDI
SCSI Controller
6
5
4
3
R677
1K
NOPOP
SCSI_SEECK
C1312
0.01UF
4
3
2
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
LAST REVISED:
Folsom, California 095630
03/04/02
2
1
D
C
B
A
SHEET
72
1

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