Intel Xeon Design Manual page 243

Processor with 512 kb l2 cache and intel e7500 chipset platform
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8
7
D
C
B
Place 100uF caps surrounding Chan B DIMMs
CAD Note: All Caps should have direct attatchment
to 2.5V plane, and 2 vias to GND.
A
8
7
6
5
DDR Channel B Series Resistors
Place near DIMM B-1
+V2_5
6
5
4
3
+V2_5
+V2_5
0.1uF Backside or Frontside Caps
6 caps between each pair of DIMMs
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
R
4
3
2
1
+V2_5
Platform Apps Engineering
1900 Prairie City Road
LAST REVISED:
Folsom, California 095630
03/04/02
2
1
D
C
B
A
SHEET
21

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