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Manuals and User Guides for Intel Xeon 7500 Series. We have
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Intel Xeon 7500 Series manual available for free PDF download: Programming Manual
Intel Xeon 7500 Series Programming Manual (146 pages)
Xeon Processor Series Uncore Programming Guide
Brand:
Intel
| Category:
Computer Hardware
| Size: 0.74 MB
Table of Contents
Table of Contents
3
Chapter 1
9
Introduction
9
Uncore Pmu Overview
9
Figure 1-1. Intel Xeon Processor 7500 Series Block Diagram
9
Uncore Pmu Summary Tables
10
Table 1-1. Per-Box Performance Monitoring Capabilities
10
Uncore Performance Monitoring Msrs
10
References
11
Chapter 2
13
Uncore Performance Monitoring
13
Global Performance Monitoring Control
13
Counter Overflow
13
Freezing on Counter Overflow
13
PMI on Counter Overflow
13
Setting up a Monitoring Session
13
Reading the Sample Interval
14
Enabling a New Sample Interval from Frozen Counters
14
Global Performance Monitors
15
Global PMON Global Control/Status Registers
15
Table 2-1. Global Performance Monitoring Control Msrs
15
Table 2-2. U_MSR_PMON_GLOBAL_CTL Register - Field Definitions
16
Table 2-3. U_MSR_PMON_GLOBAL_STATUS Register - Field Definitions
16
Table 2-4. U_MSR_PMON_GLOBAL_OVF_CTL Register - Field Definitions
16
U-Box Performance Monitoring
17
U-Box PMON Summary
17
U-Box Box Level PMON State
17
U-Box PMON State - Counter/Control Pairs
17
U-Box Performance Monitoring Msrs
17
Table 2-6. U_MSR_PMON_EVT_SEL Register - Field Definitions
17
U-Box Performance Monitoring Events
18
U-Box Events Ordered by Code
18
Table 2-7. U_MSR_PMON_CTR Register - Field Definitions
18
Table 2-8. Performance Monitor Events for U-Box Events
18
U-Box Performance Monitor Event List
19
C-Box Performance Monitoring
21
Overview of the C-Box
21
C-Box Performance Monitoring Overview
21
C-Box PMU - Overflow, Freeze and Unfreeze
21
C-BOX Performance Monitors
22
C-Box Performance Monitoring Msrs
22
C-Box Box Level PMON State
25
C-Box PMON State - Counter/Control Pairs
26
Table 2-10. C_MSR_PMON_GLOBAL_CTL Register - Field Definitions
26
Table 2-11. C_MSR_PMON_GLOBAL_STATUS Register - Field Definitions
26
Table 2-12. C_MSR_PMON_GLOBAL_OVF_CTL Register - Field Definitions
26
Table 2-13. C_MSR_PMON_EVT_SEL{5-0} Register - Field Definitions
27
Table 2-14. C_MSR_PMON_CTR{5-0} Register - Field Definitions
27
C-BOX Performance Monitoring Events
28
An Overview
28
Acronyms Frequently Used in C-Box Events
28
The Queues
29
Detecting Performance Problems in the C-Box Pipeline
29
C-Box Events Ordered by Code
29
Table 2-15. Performance Monitor Events for C-Box Events
29
C-Box Performance Monitor Event List
30
B-Box Performance Monitoring
41
Overview of the B-Box
41
B-Box Performance Monitoring Overview
41
B-Box PMU - on Overflow and the Consequences (Pmi/Freeze)
41
B-BOX Performance Monitors
42
B-Box Box Level PMON State
42
B-Box Performance Monitoring Msrs
42
B-Box PMON State - Counter/Control Pairs + Filters
43
Table 2-17. B_MSR_PMON_GLOBAL_CTL Register - Field Definitions
43
Table 2-18. B_MSR_PMON_GLOBAL_STATUS Register - Field Definitions
43
Table 2-19. B_MSR_PMON_GLOBAL_OVF_CTL Register - Field Definitions
43
Table 2-20. B_MSR_PMON_EVT_SEL{3-0} Register - Field Definitions
44
Table 2-21. B_MSR_PMON_CNT{3-0} Register - Field Definitions
44
B-Box Performance Monitoring Events
45
On the ARBQ
45
Table 2-22. B_MSR_MATCH_REG Register - Field Definitions
45
Table 2-23. B_MSR_MASK_REG Register - Field Definitions
45
On the Major B-Box Structures
46
On Invitoe Transactions
46
B-Box Events Ordered by Code
46
Table 2-24. Performance Monitor Events for B-Box Events
47
B-Box Performance Monitor Event List
48
S-Box Performance Monitoring
57
Overview of the S-Box
57
S-Box Performance Monitoring Overview
57
S-Box PMU - Overflow, Freeze and Unfreeze
57
S-BOX Performance Monitors
57
S-Box Performance Monitoring Msrs
57
S-Box PMON for Global State
58
S-Box Box Level PMON State
59
Table 2-26. S_MSR_PMON_SUMMARY Register Fields
59
Table 2-27. S_CSR_PMON_GLOBAL_CTL Register Fields
59
Table 2-28. S_MSR_PMON_GLOBAL_STATUS Register Fields
59
S-Box PMON State - Counter/Control Pairs + Filters
60
Table 2-29. S_MSR_PMON_OVF_CTRL Register Fields
60
Table 2-30. S_CSR_PMON_CTL{3-0} Register - Field Definitions
60
S-Box Registers for Mask/Match Facility
61
Table 2-31. S_CSR_PMON_CTR{3-0} Register - Field Definitions
61
Table 2-32. S_MSR_MM_CFG Register - Field Definitions
61
Table 2-33. S_MSR_MATCH Register - Field Definitions
62
Table 2-34. S_Msr_Match.opc - Opcode Match by Message Class
62
S-BOX Performance Monitoring Events
63
An Overview
63
On Queue Occupancy Usage
63
Table 2-35. S_MSR_MASK Register - Field Definitions
63
On Packet Transmission Events
64
Table 2-36. S-Box Data Structure Occupancy Events
64
S-Box Events Ordered by Code
65
Table 2-37. Performance Monitor Events for S-Box Events
65
S-Box Performance Monitor Event List
67
Figure 2-1. R-Box Block Diagram
84
R-Box Performance Monitoring
84
Overview of the R-Box
84
R-Box Input Port
84
R-Box Arbitration Control
84
R-Box Output Port
85
R-Box Link Layer Resources
85
R-Box Performance Monitoring Overview
85
Choosing an Event to Monitor - Example
85
R-Box PMU - Overflow, Freeze and Unfreeze
86
R-BOX Performance Monitors
86
R-Box Performance Monitoring Msrs
86
R-Box Performance Monitors to Port Mapping
89
R-Box Port Map
89
R-Box Box Level PMON State
90
R-Box PMON State - Counter/Control Pairs + Filters
90
Table 2-41. R_MSR_PMON_GLOBAL_CTL_{15_8, 7_0} Register Fields
90
Table 2-42. R_MSR_PMON_GLOBAL_STATUS_{15_8, 7_0} Register Fields
90
Table 2-43. R_MSR_PMON_OVF_CTL_{15_8, 7_0} Register Fields
90
Table 2-44. R_MSR_PMON_CTL{15-0} Register - Field Definitions
91
Table 2-45. R_MSR_PMON_CTL{15-8} Event Select
92
Table 2-46. R_MSR_PMON_CTL{7-0} Event Select
93
Table 2-47. R_MSR_PMON_CTR{15-0} Register - Field Definitions
93
R-Box IPERF Performance Monitoring Control Registers
94
Table 2-48. R_MSR_PORT{7-0}_IPERF_CFG{1-0} Registers
94
R-Box QLX Performance Monitoring Control Registers
95
Table 2-49. R_MSR_PORT{7-0}_QLX_CFG Register Fields
95
R-Box Registers for Mask/Match Facility
96
Table 2-51. R_MSR_PORT{7-0}_XBR_SET{2-1}_MATCH Registers
97
Table 2-52. R_MSR_PORT{7-0}_XBR_SET{2-1}_MASK Registers
98
R-BOX Performance Monitoring Events
99
An Overview
99
R-Box Events Ordered by Code
99
Table 2-53. Message Events Derived from the Match/Mask Filters
99
R-Box Performance Monitor Event List
100
Table 2-54. Performance Monitor Events for R-Box Events
100
M-Box Performance Monitoring
107
Overview of the M-Box
107
Functional Overview
107
Intel ® 7500 Scalable Memory Buffer
108
M-Box Performance Monitoring Overview
108
Choosing an Event to Monitor - Example Using Subcontrol Registers
108
M-Box PMU - Overflow, Freeze and Unfreeze
109
M-BOX Performance Monitors
110
M-Box Box Level PMON State
111
M-Box PMON State - Counter/Control Pairs
112
Table 2-64. M_MSR_PERF_GLOBAL_CTL Register Fields
112
Table 2-65. M_MSR_PERF_GLOBAL_STATUS Register Fields
112
Table 2-66. M_MSR_PERF_GLOBAL_OVF_CTL Register Fields
112
Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions
113
Table 2-68. M_MSR_PMU_CNT_{5-0} Register - Field Definitions
113
M-Box PMU Filter Registers
114
M-Box PMU Subcontrol Registers - Subunit Descriptions
114
Table 2-69. M_MSR_PMU_TIMESTAMP_UNIT Register - Field Definitions
114
Table 2-70. M_MSR_PMU_MM_CFG Register - Field Definitions
114
Table 2-71. M_MSR_PMU_ADDR_MATCH Register - Field Definitions
114
Table 2-72. M_MSR_PMU_ADDR_MASK Register - Field Definitions
114
Table 2-73. M_MSR_PMU_DSP Register - Field Definitions
116
Table 2-74. M_CSR_ISS_PMU Register - Field Definitions
116
Table 2-75. M_MSR_PMU_MAP Register - Field Definitions
117
Table 2-76. M_CSR_PMU_MA_MSC_THR Register - Field Definitions
117
Table 2-78. M_MSR_PMU_PGT Register - Field Definitions
118
Table 2-79. M_MSR_PMU_PLD Register - Field Definitions
119
Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions
120
Table 2-81. M_Msr_Pmu_Zdp_Ctl_Fvc.evnt{4-1} Encodings
120
M-Box Performance Monitoring Events
121
An Overview
121
Table 2-82. M_MSR_PMU_ZDP_CTL_FVC.RESP Encodings
121
Table 2-83. M_MSR_PMU_ZDP_CTL_FVC.BCMD Encodings
121
M-Box Events Ordered by Code
122
Table 2-84. Performance Monitor Events for M-Box Events
122
M-Box Performance Monitor Event List
123
W-Box Performance Monitoring
136
Overview of the W-Box
136
W-Box Performance Monitoring Overview
136
W-Box PMU - Overflow, Freeze and Unfreeze
136
W-BOX Performance Monitors
137
W-Box Box Level PMON State
137
Table 2-95. W_MSR_PMON_GLOBAL_CTL Register Fields
137
W-Box PMON State - Counter/Control Pairs
138
Table 2-96. W_MSR_PMON_GLOBAL_STATUS Register Fields
138
Table 2-97. W_MSR_PMON_GLOBAL_OVF_CTRL Register Fields
138
Table 2-98. W_MSR_PMON_EVT_SEL_{3-0} Register - Field Definitions
139
Table 2-99. W_MSR_PMON_FIXED_CTR_CTL Register - Field Definitions
139
W-BOX Performance Monitoring Events
140
An Overview
140
W-Box Events Ordered by Code
140
W-Box Performance Monitor Event List
140
Table 2-100. W_MSR_PMON_CTR_{3-0} Register - Field Definitions
140
Table 2-101. W_MSR_PMON_FIXED_CTR Register - Field Definitions
140
Table 2-102. Performance Monitor Events for W-Box Events
140
Packet Matching Reference
142
Table 2-103. Intel® Quickpath Interconnect Packet Message Classes
142
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