Intel Xeon Design Manual page 141

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Use of an inferior magnetics module. The magnetics modules that we use have been fully
tested for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior
magnetics modules often have less common-mode rejection and/or no auto transformer in the
transmit channel.)
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Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations
and decoupling are different. There are also differences in the receive circuit. Follow the
appropriate reference schematic or application note.
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Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45 and
for the wire-side center-taps of the magnetics modules. These unused RJ pins and wire-side
center-taps must be correctly referenced to chassis ground via the proper value resistor and a
capacitance or termplane. If these are not terminated properly, there can be emissions (FCC)
problems, IEEE conformance issues, and long cable noise (BER) problems. The application
notes have schematics that illustrate the proper termination for these unused RJ pins and the
magnetics center-taps.
Incorrect differential trace impedances. It is important to have ~100 Ω impedance between the
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two traces within a differential pair. This becomes even more important as the differential
traces become longer. It is very common to see customer designs that have differential trace
impedances between 75 Ω and 85 Ω, even when the designers think they've designed for
100 Ω. (To calculate differential impedance, many impedance calculators only multiply the
single-ended impedance by two. This does not take into account edge-to-edge capacitive
coupling between the two traces. When the two traces within a differential pair are kept close
to each other, the edge coupling can lower the effective differential impedance by 5 Ω–20 Ω. A
10 Ω–15 Ω drop in impedance is common.) Short traces will have fewer problems if the
differential impedance is a little off.
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Use of capacitor that is too large between the transmit traces and/or too much capacitance from
the magnetic's transmit center-tap (on the 82562ET side of the magnetics) to ground. Using
capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall
time so much that they fail the IEEE rise time and fall time specs. This will also cause return
loss to fail at higher frequencies and will degrade the transmit BER performance. Caution
should be exercised if a capacitor is put in either of these locations. If a capacitor is used, it
should almost certainly be less than 22 pF. (6 pF to 12 pF values have been used on past
designs with reasonably good success.) These capacitors are not necessary, unless there is
some overshoot in 100 Mbps mode.
Note: It is important to keep the two traces within a differential pair close to each other. Keeping them
close helps to make them more immune to crosstalk and other sources of common-mode noise.
This also means lower emissions (i.e., FCC compliance) from the transmit traces, and better
receive BER for the receive traces.
Note: Close should be considered to be less than 0.030 inch between the two traces within a differential
pair. 0.007 inch trace-to-trace spacing is recommended.
Design Guide
I/O Controller Hub
141