Intel Xeon Design Manual page 300

Processor with 512 kb l2 cache and intel e7500 chipset platform
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8
7
75,77
D
C
B
A
See Adaptec* AIC-7902 Design-In Handbook for
up-to-date information regarding implementation of this subsystem
8
7
6
LVD/SE Termination for SCSI Channel A
LVTRMPWR_A
Use 40 mil trace
73,77
LVMSGAP
73,77
LVCDAP
73,77
LVIOAP
73,77
LVSCDAP9
73,77
LVSCDAP11
73,77
LVSCDAP10
73,77
LVSCDAP8
73,77
LVREQAP
73,77
LVSELAP
73,77
DIFFSENSEA_R
73,77
LVSCDAP4
73,77
LVSCDAP6
73,77
LVSCDAPLP
73,77
LVACKAP
73,77
LVRSTAP
73,77
LVBSYAP
73,77
LVATNAP
73,77
LVSCDAP7
73,77
LVSCDAP5
73
CHA_TERMEN
73,77
LVSCDAP12
73,77
LVSCDAP14
73,77
LVSCDAPHP
73,77
LVSCDAP1
73,77
LVSCDAP3
73,77
LVSCDAP2
73,77
LVSCDAP0
73,77
LVSCDAP15
73,77
LVSCDAP13
6
5
4
U93
D_SNS
TPWR0
16
27
TPWR1
28
2
+R1
-R1
3
LVMSGAM
4
+R2
-R2
5
LVCDAM
7
+R3
-R3
8
LVIOAM
9
+R4
-R4
10
LVSCDAM9
11
+R5
-R5
12
LVSCDAM11
18
+R6
-R6
19
LVSCDAM10
20
+R7
-R7
21
LVSCDAM8
23
+R8
-R8
24
LVREQAM
25
+R9
-R9
26
LVSELAM
17
DIFF_CAP
HSGND2
ISO
22
13
HSGND1
M_S
6
15
GND
VREF
14
1
20 MIL trace
U94
D_SNS
TPWR0
16
27
TPWR1
28
2
+R1
-R1
3
LVSCDAM4
4
+R2
-R2
5
LVSCDAM6
7
+R3
-R3
8
LVSCDAPLM
9
+R4
-R4
10
LVACKAM
11
+R5
-R5
12
LVRSTAM
18
+R6
-R6
19
LVBSYAM
20
+R7
-R7
21
LVATNAM
23
+R8
-R8
24
LVSCDAM7
25
+R9
-R9
26
LVSCDAM5
17
DIFF_CAP
HSGND2
ISO
22
13
HSGND1
M_S
6
15
GND
VREF
14
1
20 MIL trace
U95
D_SNS
TPWR0
16
27
TPWR1
28
2
+R1
-R1
3
LVSCDAM12
4
+R2
-R2
5
LVSCDAM14
7
+R3
-R3
8
LVSCDAPHM
9
+R4
-R4
10
LVSCDAM1
11
+R5
-R5
12
LVSCDAM3
18
+R6
-R6
19
LVSCDAM2
20
+R7
-R7
21
LVSCDAM0
23
+R8
-R8
24
LVSCDAM15
25
+R9
-R9
26
LVSCDAM13
17
DIFF_CAP
HSGND2
ISO
22
13
HSGND1
M_S
6
15
GND
VREF
14
1
20 MIL trace
5
4
3
2
73,77
73,77
73,77
73,77
73,77
73,77
73,77
73,77
73,77
20MIL
73,77
73,77
73,77
73,77
73,77
73,77
73,77
73,77
73,77
R697
4.7K
20MIL
73,77
73,77
73,77
73,77
73,77
73,77
73,77
73,77
73,77
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
20MIL
Folsom, California 095630
3
2
1
D
C
B
A
SHEET
LAST REVISED:
78
03/04/02
1

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