Table of Contents
Advertisement
Layout Checklist
®
Table 14-3. Intel
ICH3-S Layout Checklist (Sheet 3 of 4)
Checklist Items
LAN Interface (Continued)
General
Guidelines
Power Decoupling
V_CPU_IO[2:0]
VCC_3.3
VCCSUS_3.3
VCC_1.8
VCCSUS_1.8
V5_REF_SUS
V5_REF
218
Recommendations
• Vias to decoupling capacitors should be
sufficiently large in diameter.
• Isolate I/O signals from high speed signals.
• Avoid routing high-speed LAN or Phone line
traces near other high-frequency signals
associated with a video controller, cache
controller, processor, or other similar device.
• Place the 82562ET/EM part more than 1.5"
away from any board edge.
• Place at least one bulk capacitor (4.7 µF or
greater OK) on each side of the 82562ET/
EM.
• Place decoupling capacitors (0.1 µF) as
close to the 82562ET/EM as possible.
• Use one 0.1 µF decoupling capacitor. Locate
within 100 mils of the ICH3-S processor
interface balls.
• Requires six 0.1 µF decoupling capacitors.
Distribute around the ICH3-S package sides
within 100 mils from the package balls:
– Top near AUX/PCI
– Left across the PCI and LPC
– Bottom near IDE.
• Requires two 0.1 µF decoupling capacitors.
Place one capacitor on the top side within
200 mils of the USB center. Place other on
bottom side near the VCCSus3_3 supply.
• Requires four 0.1 µF decoupling capacitors.
Locate two capacitors distributed local to the
hub interface; within 50 mils of the package
hub interface balls. Distribute remaining
capacitors on the left and bottom sides of the
package for core delivery.
• Requires one 0.1 µF decoupling capacitor.
Locate within 200 mils of balls B23 and C23
of the
ICH3-S.
• Requires one 0.1 µF decoupling
capacitor.V5_REF_Sus affects only 5 V-
tolerance for USB OC[5:0]# balls, and can
be connected to VCCSus3_3 if 5 V tolerance
on these signal is not required.
• Requires one 0.1 µF decoupling capacitor.
V5REF is the reference voltage for 5V
tolerant inputs in the ICH3-S. Tie to balls
V5REF[2:1]. V5REF must power up before
or simultaneous to VCC3_3. It must power
down after or simultaneous to VCC3_3.
Comments
• To decrease series inductance.
• To minimize crosstalk.
• To minimize crosstalk.
• This minimizes the potential for
EMI radiation problems.
• Research and development has
shown that this is a robust design
recommendation.
• Used to pull-up all processor I/F
signals.
Design Guide
Advertisement
Table of Contents
