Intel Xeon Design Manual page 225

Processor with 512 kb l2 cache and intel e7500 chipset platform
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8
7
Page 47
133MHz
PCI-X Slot1
D
Pages 69-71
Intel(R)
82544EI
LAN controller
100MHz
Device A
Page 42
Page 48
Bus
PCI-X Slot2
Switches
Device B
C
Page 76
SCSI
Controller
133MHz
PCI-X
Pages 43-46
66MHz
Bus
PCI-X
Switches
B
PCI-X Slots A:D
Pages 49-52
PCI-X Slot D extension
A
8
7
6
PCI-X
Pages 27-30
Bus A
Intel (R)
82870P2
PCI-X
(P64H2)
# 1
Bus B
Hot Plug
Logic
Pages 37,39
Pages 31-34
Bus A
P64H2
# 2
Bus B
Hot Plug
Logic
Pages 38,40,41
PS2 KB/Mouse
Simplified System Block Diagram
6
5
4
Pages 4-9
INTEL(R) XEON(TM) PROCESSOR
WITH 512KB L2 CACHE
HI 2.0
HI 2.0
E7500 Chipset
Memory Controller Hub
HI 2.0
HI 1.5
Pages 58-59
On board
33MHz PCI
PCI Video
I/O Controller Hub
Page 57
32-bit PCI Slot
For Debug Only
Super I/O
Pages 67-68
Serial /
Floppy
Parallel
5
4
3
2
INTEL(R) XEON(TM) PROCESSOR
WITH 512KB L2 CACHE
Pages 10-14
DDR DIMM
Intel(R)
Pages 15-26
(MCH)
DDR DIMM
SMBus
Intel(R)
82801CA
USB Ports
(ICH3-S)
Pages 53-56
IDE Port
SMBus
LPC
FWH
Page 66
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
Folsom, California 095630
3
2
1
D
C
B
A
SHEET
LAST REVISED:
3
03/04/02
1

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