Intel Xeon Design Manual page 208

Schematic Checklist
®
Table 13-4. Intel P64H2 Schematic Checklist (Sheet 5 of 5)
Checklist Items
Hot Plug – Disabled
HPxSLOT[2:0]
HPx_SID
HPx_SIC
HPx_SIL#
HPx_SOR#
HPx_SORR#
HPx_SOC
HPx_SOL
HPx_SOLR
HPx_SOD
PCIXCAP
SMBus Interface
SDTA
SCLK
Power
VCC
VCC1.8
VCC3.3
VCC5REF
Miscellaneous Signals
TP0
RSTIN#
TEST#
RASERR#
NOTE:
1. x = A or B
208
Recommendations
• If disabling hot plug mode, connect these
signals to ground through an 8.2 k Ω ± 5%
resistor.
• Connect to ground through an 8.2 k Ω ± 5%
resistor.
• If disabling hot plug mode, these signals can
be left as no connect.
• This signal does not need a pull-up or a pull-
down resistor when hot plug is disabled.
• Use an 8.2 k Ω ± 5% pull-up resistor to
VCC_3.3.
• Connect to 1.8 V power supply.
• Decoupling:
– 8 X 0.1 µF capacitors near the P64H2.
– 2 X 4.0 µF capacitors near regulator.
• Connect to 1.8 V Power Supply.
• Decoupling:
– 2 X 1.0 µF capacitors near the P64H2.
– 1 X 100.0 µF capacitors near regulator.
• Connect to 3.3 V Power Supply.
• Decoupling;
– 20 0.1 µF capacitors near the P64H2.
– 6 X 1.0 µF capacitors near the P64H2.
– 2 X 4.0 µF capacitors near regulator.
– 1 X 100.0 µF capacitors near regulator.
• Connect to 5 V Power Supply.
• 8.2 k Ω ± 5% pull-up resistor to VCC3.3.
• Connect to the PCIRST# output of the
ICH3-S.
• 8.2 k Ω ± 5% pull-up resistor to VCC3.3.
• 8.2 k Ω ± 5% pull-up resistor to VCC3.3.
Comments
• HPxSLOT[2:0] signals should
be strapped to zero to disable
hot plug mode.
• Unused inputs should not float.
• 1.8 V Core Voltage.
• 1.8 V Hub Interface Voltage.
• 3.3 V.
• 5 V.
• Reset In. When asserted, this
signal asynchronously resets
the P64H2 logic and asserts
PCIRST# active output from
each PCI interface.
• Intel Test Mode.
Design Guide