Intel Xeon Design Manual page 296

Processor with 512 kb l2 cache and intel e7500 chipset platform
Hide thumbs Also See for Xeon:
Table of Contents

Advertisement

8
7
SCSI_VCC
76
D
C
B
See Adaptec* AIC-7902 Design-In Handbook for
up-to-date information regarding implementation of this subsystem
A
8
7
6
5
C1316
C1315
C1425
+
2
1
0.01UF
0.01UF
10UF
C1313
C1422
C1423
+
+
0.01UF
2
1
2
1
10UF
10UF
SCSI PWR/GND
SCSI Controller
6
5
4
3
C1426
2
10UF
C1314
0.01UF
C1317
C1424
0.01UF
+
2
1
10UF
4
3
2
SCSI_CORE_VCC
75,76
C1427
+
+
1
2
1
10UF
C1318
0.01UF
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
LAST REVISED:
Folsom, California 095630
2
1
D
C
B
A
SHEET
74
03/04/02
1

Advertisement

Table of Contents
loading

Table of Contents