Intel Xeon Design Manual page 285

Processor with 512 kb l2 cache and intel e7500 chipset platform
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8
7
D
C1561
C1549
C1563
C1559
C1562
Small Signal
Ground
C
between pins 5,6
B
A
8
7
6
V1.2 Regulation
+V5_0
1_2_LT1735_PGOOD
62
C1548
R813
Q49
1M
4
G
LTC1735_1-SL25099
1
16
COSC
TG
2
15
RUN/SS
BOOST
3
14
ITH
SW
4
13
SCHOTTKY
PGOOD
VIN
C1564
5
12
SENSE-
INTVCC
6
11
0.22UF
SENSE+
BG
CR78
C1547
7
10
VOSENSE
PGND
Place C1547
8
9
close to pins 10,12
SGND
EXTVCC
U115
C1552
0.1UF
C1560
Place C1560
Q50
4
G
6
5
4
+V5_0
Place caps close to FET
5
6
7
8
D
S
3
2
1
L22
R814
V1_2_L
1
2
1.0UH
0.010
Route as
diff pair
V1_2SENSE_P
V1_2SENSE_N
5
6
7
8
D
1
S
2
3
2
1
5
4
3
2
+V1_2
TITLE:
INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS
Platform Apps Engineering
R
1900 Prairie City Road
Folsom, California 095630
3
2
1
D
C
B
A
SHEET
LAST REVISED:
63
03/04/02
1

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