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E
A.37
LOCK# (I/O)
The LOCK# signal is the Arbitration group bus lock
signal. For a locked sequence of transactions,
LOCK# is asserted from the first transaction's
Request Phase through the last transaction's
Response Phase. A locked operation can be
prematurely aborted (and LOCK# deasserted) if
AERR# or DEFER# is asserted during the first bus
transaction of the sequence. The sequence can also
be prematurely aborted if a hard error (such as a
hard failure response or AERR# assertion beyond
the retry limit) occurs on any one of the transactions
during the locked operation.
When the priority agent asserts BPRI# to arbitrate for
bus ownership, it waits until it observes LOCK#
deasserted. This enables symmetric agents to retain
bus ownership throughout the bus locked operation
and guarantee the atomicity of lock. If AERR# is
asserted up to the retry limit during an ongoing
locked operation, the arbitration protocol ensures that
the lock owner receives the bus ownership after
arbitration logic is reset. This result is accomplished
by requiring the lock owner to reactivate its
arbitration request one clock ahead of other agents'
arbitration
request.
LOCK#
throughout the arbitration reset sequence.
A.38
NMI (I)
The NMI signal is the Non-maskable Interrupt signal.
It is the state of the LINT1 signal when APIC is
disabled. Asserting NMI causes an interrupt with an
internally supplied vector value of 2. An external
interrupt-acknowledge transaction is not generated. If
NMI is asserted during the execution of an NMI
service routine, it remains pending and is recognized
after the IRET is executed by the NMI service
routine. At most, one assertion of NMI is held
pending.
NMI is rising-edge sensitive. Recognition of NMI is
guaranteed in a specific clock if it is asserted
synchronously and meets the setup and hold times. If
asserted asynchronously, active and inactive pulse
PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
widths must be a minimum of two clocks. In FRC
mode, NMI must be synchronous to BCLK.
A.39
The PICCLK signal is the Execution Control group
APIC Clock signal. It is an input clock to the Pentium
Pro processor for synchronous operation of the APIC
bus. PICCLK must be synchronous to BCLK in FRC
mode.
A.40
The PICD[1:0] signals are the Execution Control
group APIC Data signals. They are used for bi-
directional serial message passing on the APIC bus.
A.41
PWRGOOD is driven to the Pentium Pro processor
by the system to indicate that the clocks and power
supplies
Section 3.9 for additional details. This signal will not
is
kept
asserted
affect FRC operation.
A.42
The REQ[4:0]# signals are the Request Command
signals. They are asserted by the current bus owner
in both clocks of the Request Phase. In the first
clock, the REQa[4:0]# signals define the transaction
type to a level of detail that is sufficient to begin a
snoop request. In the second clock, REQb[4:0]#
signals carry additional information to define the
complete transaction type. REQb[4:2]# is reserved.
REQb[1:0]# signals transmit LEN[1:0]# (the data
transfer
REQ[4:0]# and ADS# are protected by parity RP#.
All receiving agents observe the REQ[4:0]# signals
to determine the transaction type and participate in
the transaction as necessary, as shown in Table 53.
PICCLK (I)
PICD[1:0] (I/O)
PWRGOOD (I)
are
within
their
specification.
REQ[4:0]# (I/O)
length
information).
In
See
both
clocks,
109
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