Ppc Master - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2

PPC Master

2-10
For example, two burst transactions would make the data FIFO the limiting
factor for write posting. Four single beat transactions would make the
command FIFO be the limiting factor. If either limit is exceeded, then any
pending PPC transactions will be delayed (AACK_ and TA_ will not be
asserted) until the PCI Master has completed a portion of the previously
posted transactions and created some room within the command and/or
data FIFOs.
The PHB does not support byte merging or byte collapsing. Each and
every single beat transaction presented to the PPC Slave will be presented
to the PCI bus as a unique single beat transfer.
The PPC Master can transfer data either in 1-to-8 byte single beat
transactions or 32 byte, four beat burst transactions. This limitation is
strictly imposed by the PPC60x bus protocol. The PPC Master will attempt
to move data using burst transfers whenever possible. If a transaction starts
on a non-cache line address, the PPC Master will perform as many single
beat transactions as needed until the next highest cache line boundary is
reached. If a write transaction ends on a non-cache line boundary, then the
PPC Master will finish the transaction with as many single beat
transactions as needed to complete the transaction.
Table 2-2 shows the relationship between starting addresses and PPC60x
bus transaction types when write posting and read ahead are enabled.
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