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CHAPTER 15 MULTI-PULSE GENERATOR
■ OPDR Register Write Timing Diagram (OPS2 to OPS0 = 000
Figure 15.6-6 OPDR Register Write Timing Diagram (OPS2 to OPS0 = 000
OPS2 to OPS0
RDA2 to RDA0
(OPDR)
OPDBR0W
OPDBR1W
OPDBR0[0]
OPDBR1[0]
WTO
OP00
■ Signal Flow Diagram for Reload Timer 0 Underflow by Setting OPS2 to OPS0 = 001
Figure 15.6-7 Signal Flow Diagram for Reload Timer 0 Underflow (OPS2 to OPS0 = 001
16-BIT RELOAD TIMER 0
OPDBR0 WRITE SIGNAL
SNI2 to
Pin
SNI0
The 16-bit reload timer 0 can be triggered by both TIN input and software to generate the write signal at
this setting. The write signal is controlled by the 16-bit reload timer 0 underflow.
402
101
TIN
TOUT
POSITION
DETECTION
000
001
TIN0O
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
)
B
)
B
B
Pin
TIN0
WRITE
WTO
TIMING
OUTPUT
B
)
TIN0
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