Division Rate Control Register (Div0/Div1) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 16 PWC Timer
16.4.3

Division Rate Control Register (DIV0/DIV1)

The division rate control register (DIV0/DIV1) is used in the division period
measurement mode (PWCSL:MOD2, 1, and 0 = 011
other modes.
■ Division Rate Control Register (DIV0/DIV1)
Address bit 7
ch.0: 00000C
H
—
ch.1: 00002C
H
—
X : Indeterminate
R/W : Read and write
: Initial value
— : Not used
Table 16.4-3 Division Rate Control Register (DIV0/DIV1)
Bit name
bit7
to Unused bit
bit2
bit1, DIV1,DIV0:
bit0 Division rate selection bits
444
Figure 16.4-5 Division Rate Control Register (DIV0/DIV1)
6 5 4 3
— — — —
— — — —
• The read value is indeterminate.
• Writing to these bits has no effect on the operation.
• In the division range measurement mode, this register is used to divide the pulse input
from the measurement pin and measure the one-period width after division.
• After reset, these bits are initialized to "00
(Note)
After the timer starts, the setting cannot be changed. Write these bits before the
timer has started or after the timer has stopped.
). This register has no meaning in
B
2 1 0 Initial value
------00
DIV1 DIV0
—
— R/W R/W
DIV1 DIV0 Division rate selection bits
0 0
0 1
1 0
1 1
Function
". These bits can be read and written.
B
B
2
2 = divided by 4
4
2 = divided by 16
6
2 = divided by 64
8
2 = divided by 256