Fujitsu MB90460 Series Hardware Manual page 346

■ Compare Clear Buffer
There is a selected buffer function on compare clear register (CPCLR). In buffer enable (TCCSL:BFE=1),
data written in compare clear buffer register (CPCLRB) will transfer to CPCLR at zero detection of the 16-
bit free-run timer. In buffer disable (TCCSL:BFE=0), CPCLRB is transparent, data can directly be written
into CPCLR.
Figure 14.6-3 Operation in Up-count Mode with Compare Clear Buffer is disabled (TCCSL:BFE=0)
Counter value
FFFF
H
BFFF
7FFF
H
3FFF
H
0000
H
Reset
Compare clear
buffer register
value
Compare clear
register value
Figure 14.6-4 Operation in Up-count Mode with Compare Clear Buffer is enabled (TCCSL:BFE=1)
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Compare clear
buffer register
value
Compare clear
register value
H
Timer starts
Zero detect
BFFF
BFFF
Timer starts
Zero detect
BFFF
H
BFFF
H
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Zero detect
7FFF
H
H
7FFF
H
H
Zero detect
FFFF
7FFF
H
7FFF
H
FFFF
H
FFFF
H
H
FFFF
H
Time
Time
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