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14.4.8
16-bit Timer Register (TMRR0/TMRR1/TMRR2)
16-bit timer registers hold the compare value of 16-bit timers.
■ 16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
Figure 14.4-19 16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
16-bit Timer Register (Upper)
Address: ch.0 000051
ch.1 000053
ch.2 000055
Read/write
Initial value
16-bit Timer Register (Lower)
Address: ch.0 000050
ch.1 000052
ch.2 000054
Read/write
Initial value
These registers are used to store the comparison value of 16-bit timers. The value in these registers will be
reloaded when the 16-bit timer is started to operate. Therefore, if the value is re-written into these registers
during timer operation, these value will be valid at the next timer initiation/operation.
In dead-time timer mode, these registers are used to set the non-overlap time.
• Non-overlap time = (set value + 1) × selected clock.
Notes:
• The value of "0000
• The maximum offset of non-overlap time is -1 selected clock.
In timer mode, these registers are used to set the GATE time for PPG timer 0 operation.
• GATE time = (set value + 1) × selected clock.
Notes:
• The value of "0000
• The maximum offset of GATE time is -1 selected clock.
bit
15
14
H
H
TR15
TR14
TR13
H
R/W
R/W
R/W
X
X
X
7
6
bit
H
H
TR07
TR06
TR05
H
R/W
R/W
R/W
X
X
" cannot be set.
H
" cannot be set and maximum offset is -1 selected clock.
H
CHAPTER 14 MULTI-FUNCTIONAL TIMER
13
12
11
TR12
TR11
TR10
R/W
R/W
R/W
X
X
X
5
4
3
TR04
TR03
TR02
R/W
R/W
R/W
X
X
X
X
10
9
8
TMRR0/TMRR1/
TMRR2
TR09
TR08
R/W
R/W
X
X
2
1
0
TMRR0/TMRR1/
TR01
TR00
TMRR2
R/W
R/W
X
X
313
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