Fujitsu MB90460 Series Hardware Manual page 732

PWC Control Status Register
PWC Control Status Register,Upper Byte
(PWCSH0/PWCSH1).......................... 439
PWC control Status Register
PWC control Status Register,Lower Byte
(PWCSL0/PWCSL1)........................... 441
PWC Data Buffer Register
PWC Data Buffer Register (PWC0/PWC1) ........ 443
PWC Timer
Block Diagram of the PWC Timer Pins.............. 436
2
OS Function of the PWC Timer.................... 446
EI
PWC Timer (×2,PWC Timer 0 is not present in
MB90465 Series) ................................ 434
PWC Timer Block Diagram .............................. 435
PWC Timer Interrupts ...................................... 445
PWC Timer Interrupts and EI
PWC Timer Pins .............................................. 436
PWC Timer Registers....................................... 438
Sample Program for the PWC Timer.................. 464
Usage Notes on the PWC Timer ........................ 461
PWCSH
PWC Control Status Register,Upper Byte
(PWCSH0/PWCSH1).......................... 439
PWCSL
PWC control Status Register,Lower Byte
(PWCSL0/PWCSL1)........................... 441
PWM
PWM Mode (PCNTL: MDSE=0) ...................... 273
PWM Mode
PWM Mode (PCNTL: MDSE=0) ...................... 273
R
RAM
RAM Area ........................................................ 30
Storage of Multi-byte Data in RAM ..................... 37
Read
Setting the Read/Reset Status ............................ 601
Reception Interrupt
Reception Interrupt Generation and Flag Set Timing
.......................................................... 488
Register
16-bit Reload Register (TMRD0/TMRD1) ......... 242
16-bit Timer Control Register (DTCR0/DTCR2)
.......................................................... 314
16-bit Timer Control Register (DTCR1)............. 316
16-bit Timer Register (TMR0/TMR1) ................ 241
A/D Control Status Register 0 (ADCS0) ............ 551
A/D Control Status Register 1 (ADCS1) ............ 549
A/D Data Register (ADCR0/ADCR1) ................ 554
Communication Prescaler Control Register (CDCR)
.......................................................... 484
Compare Clear Buffer Register (CPCLRB) ........ 293
Compare Clear Register (CPCLR) ..................... 293
Compare Clear Register (CPCR) ....................... 388
2
OS...................... 445
Compare Control Register,Upper Byte
(OCS1/OCS3/OCS5) ...........................301
Condition Code Register (CCR) Configuration......48
Control Status Register (FMCS).........................590
Delayed Interrupt Generator Module Register (DIRR)
..........................................................537
Direct Page Register (DPR) .................................53
Division Rate Control Register (DIV0/DIV1)
..........................................................444
DTP/interrupt Cause Register (EIRR) .................521
DTP/interrupt Enable Register (ENIR) ...............522
Input Capture Control Status Register,Lower Byte
(ICSL23) ............................................307
Input Capture Control Status Register,Lower Byte
(PICSL01) ..........................................311
Input Capture Control Status Register,Upper Byte
(ICSH23) ............................................306
Input Capture Register (IPCP0 to IPCP3)............305
Input Control Lower Register (IPCLR) ...............386
Input Control Upper Register (IPCUR) ...............384
Input Data Register (SIDR0/SIDR1)...................482
Interrupt Level Mask Register (ILM)....................51
Noise Cancellation Control Register (NCCR)
..........................................................392
Output Control Lower Register (OPCLR) ...........374
Output Control Upper Register (OPCUR) ...........372
Output Data Buffer Lower Register (OPDBR)
..........................................................382
Output Data Buffer Upper Register (OPDBR)
..........................................................380
Output Data Lower Register (OPDR) .................378
Output Data Register (OPDR)............................398
Output Data Register (SODR0/SODR1) .............482
Output Data Register Block Diagram..................397
Output Data Upper Register (OPDR)..................376
PPG Control Status Register,Lower Byte
(PCNTL0 to PCNTL2).........................269
PPG Control Status Register,Upper Byte
(PCNTH0 to PCNTH2) ........................267
PPG Down Counter Register (PDCR0 to PDCR2)
..........................................................264
PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
..........................................................266
PPG Output Control/Input Capture Control Status
Register,Upper Byte (PICSH01)............309
PPG Period Setting Buffer Register (PCSR0 to
PCSR2) ..............................................265
Program Address Detection Control Status Register
(PACSR) ............................................576
Program Address Detection Register 0/1
(PADR0/PADR1) ................................575
PWC control Status Register,Lower Byte
(PWCSL0/PWCSL1) ...........................441
PWC Control Status Register,Upper Byte
(PWCSH0/PWCSH1) ..........................439
PWC Data Buffer Register (PWC0/PWC1) .........443
Request Level Setting Register (ELVR)..............524
INDEX
713