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CHAPTER 7 INTERRUPT
■ Hardware Interrupt Operation
Figure 7.4-2 shows hardware interrupt operation from generation of a hardware interrupt to the completion
of interrupt processing.
IL:
PS:
I:
ILM:
IR:
FF:
(1) An interrupt cause is generated within the peripheral function.
(2) The interrupt enable bit of the peripheral function is referenced. If the interrupt is enabled, the
interrupt request is output from the peripheral function to the interrupt controller.
(3) The interrupt controller that receives the interrupt request determines the priority of simultaneous
interrupt requests, then transfers the interrupt level (IL) that matches the corresponding interrupt
request to the CPU.
(4) The CPU compares the interrupt level (IL) requested by the interrupt controller with the interrupt level
mask register (ILM).
(5) If the comparison indicates a higher priority than the current interrupt processing level, the CPU checks
the contents of the I flag in the condition code register (CCR).
(6) If in the check in (5) the I flag is interrupt enabled (I = 1), the CPU waits until the execution of the
instruction currently being executed terminates. At termination, the CPU sets the requested level (IL)
in the ILM.
(7) Registers are saved, and processing branches to the interrupt processing routine.
(8) The interrupt cause that was generated in (1) is cleared by software in the interrupt processing routine.
Execution of the RETI instruction terminates the interrupt processing.
130
Figure 7.4-2 Hardware Interrupt Operation
Internal bus
Microcode
X
Other peripheral
functions
Peripheral function that generated
the interrupt request
Enable FF
Factor FF
Interrupt level setting bit in the interrupt control register (ICR)
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
Check
Comparator
Level
Interrupt
comparator
level IL
Interrupt controller
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