Fujitsu MB90460 Series Hardware Manual page 429

F2mc-16lx 16-bit microcontroller
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CHAPTER 15 MULTI-PULSE GENERATOR
The data transfer from the Output Data Buffer Register (OPDBR) specified by the BNKF, RDA2 to RDA0
bits to the Output Data Register (OPDR) is updated automatically whenever a 16-bit reload timer 0
underflow is generated as shown in Figure 15.6-15.
In order to use this method, the reload timer should be used in "Reload Mode". Software trigger is needed
to be used for the startup of the reload timer. The 16-bit reload timer 0 is needed for setting the update time
in advance and executing the continuous control action.
■ Timing Generated by Reload Timer Underflow (OPS2 to OPS0 = 001
Figure 15.6-15 Timing Generated by Reload Timer Underflow (OPS2 to OPS0 = 001
Reload
timer 0
counter
action
RDA2 to
100
RDA0
(OPDR)
WTIN0
(TOUT)
WTO
OP01,
00
OP00
(OPDR)
PPG
OPT0
410
110
101
01
11
)
B
011
001
00
10
)
B

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