Output Data Buffer Register (Opdbr) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 15 MULTI-PULSE GENERATOR
15.4.3

Output Data Buffer Register (OPDBR)

The Output Data Buffer Register is composed of twelve registers (OPDBRB to
OPDBR0). The value of the OPDBRx register specified by the BNKF, RDA2 to RDA0 bits
is loaded into the OPDR register at the rising edge of the write signal generated by the
Data Write Control Unit.
■ Output Data Buffer Upper Register (OPDBR)
Address bit 15
003FF7
H
BNKF
to 003FE1
H
R/W
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used
380
Figure 15.4-6 Output Data Buffer Upper Register (OPDBR)
14 13 12 11
RDA2 RDA1 RDA0 OP51
R/W R/W R/W R/W
BNKF RDA2 RDA1 RDA0
0
0
0
0
0
0
0
0
1
1
1
1
10 9 8 Initial value
OP50 OP41 OP40 00000000
R/W R/W R/W
OP41 OP40 OPT4 output waveform selection bits
0 0 Setting for OPT4 pin to output "L" level.
Setting for OPT4 pin to output the output of
0 1
the PPG timer.
Setting for OPT4 pin to output the inverted
1 0
output of the PPG timer.
1 1
Setting for OPT4 pin to output "H" level.
OP51 OP50 OPT5 output waveform selection bits
0 0 Setting for OPT5 pin to output "L" level.
Setting for OPT5 pin to output the output of
0 1
the PPG timer.
Setting for OPT5 pin to output the inverted
1 0
output of the PPG timer.
1 1
Setting for OPT5 pin to output "H" level.
0 0 0 Set OPDBR0 as next to be loaded to OPDR.
0 0 1
Set OPDBR1 as next to be loaded to OPDR.
0 1 0
Set OPDBR2 as next to be loaded to OPDR.
0 1 1
Set OPDBR3 as next to be loaded to OPDR.
1 0 0
Set OPDBR4 as next to be loaded to OPDR.
1 0 1
Set OPDBR5 as next to be loaded to OPDR.
1 1 0
Set OPDBR6 as next to be loaded to OPDR.
1 1 1
Set OPDBR7 as next to be loaded to OPDR.
0 0 0
Set OPDBR8 as next to be loaded to OPDR.
0 0 1
Set OPDBR9 as next to be loaded to OPDR.
0 1 0
Set OPDBRA as next to be loaded to OPDR.
0 1 1
Set OPDBRB as next to be loaded to OPDR.
Prohibited.
Other values
B
OPDBR register selection bits