Fujitsu MB90460 Series Hardware Manual page 330

■ Input Capture Control Status Register, Lower Byte (PICSL01)
Figure 14.4-18 Input Capture Control Status Register (PICSL01)
Address bit7
000068 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00000000
H
R/W R/W
R/W : Read and Write
: Initial value
6 5 4 3
R/W R/W R/W
CHAPTER 14 MULTI-FUNCTIONAL TIMER
2 1 0 Initial value
R/W R/W R/W
EG01 EG00
0 0
0 1
1 0
1 1
EG11 EG10
0 0
0 1
1 0
1 1
ICE0 Interrupt request enable bit (input capture 0)
0
1
ICE1 Interrupt request enable bit (input capture 1)
0
1
Interrupt request flag bit (input capture 0)
ICP0
Read
0 No valid detected
1 Valid detected
Interrupt request flag bit (input capture 1)
ICP1
Read
0 No valid edge detected
1 Valid edge detected
B
Edge selection bit (input capture 0)
No edge detection (stop)
Rising edge detection
Falling edge detection
Both edges detection
Edge selection bit (input capture 1)
No edge detection (stop)
Rising edge detection
Falling edge detection
Both edges detection
Disable interrupt request
Enable interrupt request
Disable interrupt request
Enable interrupt request
Write
Clear this bit
No effect
Write
Clear this bit
No effect
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