Fujitsu MB90460 Series Hardware Manual page 155

F2mc-16lx 16-bit microcontroller
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CHAPTER 7 INTERRUPT
Interrupt handling time (φ machine cycle)
The CPU saves dedicated registers to the system stack and fetches interrupt vectors after it receives an
interrupt request. The required handling time for this processing is f machine cycles. The interrupt
handling time is calculated with the following formula:
When an interrupt is activated: θ = 24 + 6 + Z machine cycles
When control is returned from an interrupt: θ = 11 + 6 + Z machine cycles (RETI instruction)
The interrupt handling time is different for each address pointed to by the stack pointer.
Table 7.4-3 shows the interpolation values (Z) for the interrupt handling time.
Table 7.4-3 Interpolation Values (Z) for the Interrupt Handling Time
External 8-bit
External even-numbered address
External odd-numbered address
Internal even-numbered address
Internal odd-numbered address
Reference:
One machine cycle corresponds to one clock cycle of the machine clock (φ).
136
Address pointed to by the stack pointer
Interpolation value (Z)
+4
+1
+4
0
+2

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